1. Field of the Invention
The present invention relates generally to display apparatus and, more particularly, is directed to a display apparatus that is suitably applied to a display panel apparatus in which a number of liquid crystals or a number of fluorescent phosphor tubes are arranged in a two-dimensional manner or in an X-Y matrix shape.
2. Description of the Prior Art
In order to understand the present invention more clearly, a prior-art display apparatus utilizing, for example, a liquid crystal display panel will be described hereinunder with reference to FIG. 1. FIG. 1 shows an overall arrangement of a prior-art display apparatus.
Referring to FIG. 1, it will be seen that a video signal applied to a video input terminal 1 is supplied to a luminance signal (Y) and chroma signal (C) separating circuit (Y/C separating circuit) 2 which processes the video signal to provide a luminance signal Y and a chroma signal C. The video signal applied to the input terminal 1 is also supplied to a synchronizing separating circuit 3, from which there are derived a horizontal synchronizing signal HD which separates the respective lines of successive frames of the television image, and a synchronizing signal SYNC, respectively. The luminance signal Y, the chrominance signal C, the horizontal synchronizing signal HD and the synchronizing signal SYNC are all supplied to an RGB decoder 4 which generates red, green and blue three primary color signals R, G and B. The red, green and blue primary color signals R, G and B are respectively supplied to amplifiers 5R, 5G and 5B which generate signals of positive and negative polarities. These signals of positive and negative polarities are supplied to an alternate current drive switch 6.
A composite synchronizing signal from the separating circuit 3 is supplied to a display panel control signal generating circuit 7, whereby the display panel control signal generating circuit 7 supplies a field pulse which inverts its polarity at every field to the switch 6. The switch 6 generates as a result red, green and blue signals R, G and B which are made alternate current signals at every field. The red, green and blue signals R, G and B from the switch 6 are supplied to a data driver 8.
The data driver 8 is also supplied with a picture element clock signal, a reset signal, a transfer timing signal and an output timing signal from the generating circuit 7 in synchronism with the horizontal synchronizing signal. These signals are supplied through gate circuits 9a, 9b, 9c and 9d to the data driver 8. The generating circuit 7 supplies a reset signal synchronized with a vertical synchronizing signal to a scan driver 10, and also supplies a horizontal synchronizing signal HD through a gate circuit 11 to the scan driver 10. The data driver 8 and the scan driver 10 drive a display panel 12, whereby the video signal applied to the terminal 1 is sampled at every pixel by the data driver 8 and is supplied to the display panel 12 in response to the transfer timing signal and to the output timing signal, while the scan driver 10 sequentially selects the respective horizontal scanning lines, thereby displaying a video image on the display panel 12.
In the prior-art display apparatus as described above, it is proposed that the display panel 12 might have 512 display scanning lines which correspond to an effective picture area according, for example, to the NTSC system.
It is also proposed to produce this kind of display apparatus which displays a video signal according to the CCIR system. The effective picture area according to the CCIR system has more than 600 display scanning lines, and in the manufacturing-process of this kind of display panel, the yield of such display panel is not satisfactory. In addition, the demand for the display panel according to the CCIR system is expected to be very small as compared with the display panel according to the NTSC system.
In order to solve the above-mentioned problem, it is proposed that a video image according to the CCIR system is displayed on the above-mentioned display panel of the NTSC system. According to this proposal, a ratio between the CCIR and NTSC horizontal scanning lines is about 6:5, whereby the video image according to the CCIR system can be displayed on the display panel according to the NTSC system by throwing away or deleting the horizontal scanning lines of the video image according to the CCIR system at the ratio of 1:6.
To meet this proposal, as shown in FIG. 1, the generating circuit 7 supplies the horizontal synchronizing signal HD and the reset signal synchronized with the vertical synchronizing signal to a counter 13, and the output signal from the counter 13 is used to control the gate circuits 9a to 9d and the gate circuit 11. The counter 13 effects the above removal of the horizontal scanning lines, and will be described more fully with reference to a block diagram forming FIG. 2. In FIG. 2, like parts corresponding to those of FIG. 1 are marked with the same references and therefore need not be described in detail.
Referring to FIG. 2, it will be seen that the horizontal synchronizing signal HD from the generating circuit 7 (FIG. 1) is supplied to a terminal 21. The signal from the terminal 21 is supplied through an inverter 22 to a clock input terminal CK of a 16-scale counter 23. The waveform of the signal applied to the terminal 21 is shown in FIG. 3A. The reset signal synchronized with the vertical synchronizing signal is supplied to a terminal 24 from the generating circuit 7 (shown in FIG. 1), and the reset signal from the terminal 24 is fed to a D input terminal of a D flip-flop 25. The waveform of the reset signal is illustrated in FIG. 3B. Also, a clock signal having a frequency of, for example, 4 MHz applied to a terminal 26 is supplied to a clock input terminal CK of the D flip-flop 25. The output signal developed at the Q output terminal of the D flip-flop 25 and the reset signal from the terminal 24 are supplied to a NAND circuit 27. The output (whose waveform is illustrated in FIG. 3C) from the NAND circuit 27 is fed to the clear input terminal CL of the counter 23. Of the data input terminals A to D of the counter 23, a signal of "0" (low level) is supplied to the data input terminal A (least significant bit) and to the data input terminal C, whereas a signal of "1" (high level) is supplied to the data input terminal B and to the data input terminal D (most significant bit). Data [10] (decimal value) is therefore inputted to the counter 23. The carry output of the counter 23 is supplied through an inverter 28 to the load input terminal LOAD of the counter 23.
According to the circuitry shown in FIG. 2, when the horizontal synchronizing signal HD shown in FIG. 3A is supplied to the terminal 21 and the reset signal shown in FIG. 3B is supplied to the terminal 24, the NAND circuit 27 derives the clear signal whose waveform is shown in FIG. 3C. The signal from the NAND circuit 27 is supplied to the clear terminal CL of the counter 23, whereby the counter 23 derives a carry output when counting the horizontal synchronizing signal HD from the terminal 21 16 counts after having received the signal at its clear input terminal CL. Further, when this carry output is supplied to the load input terminal LOAD of the counter 23, the data of [10] is loaded to the counter 23. Then, the counter 23 therefore generates the carry output each time it counts the signal from the terminal 21 6 times as shown in FIG. 3D.
When the carry output and the signal from the terminal 21 are supplied to the gate circuit (NOR circuit) 11, the NOR circuit 11 generates at its output terminal 11' the horizontal synchronizing signal HD from which every sixth whose pulse is removed as shown by a phantom pulse in FIG. 3A.
The thus processed horizontal synchronizing signal HD is supplied to the scan driver 10 (shown in FIG. 1), whereby during the period of the thus removed horizontal synchronizing signal, the horizontal scanning position of the display panel 12 is not advanced and the signals from the data driver 8 are neglected, thus resulting in the pulse of the horizontal synchronizing signal being removed (scanning line is converted). In that event, the supply of the clock signal, the reset signal, the transfer timing signal and the output timing signal from the generating circuit 7 to the data driver 8 is stopped by the gate circuits 9a to 9d, whereby a disturbance can be prevented from being caused by an undesired signal.
In this way, the video image according to the CCIR system can be displayed on the NTSC display panel by removing the scanning lines at the ratio of 1:6.
In a case of the above-mentioned display apparatus, the position of the horizontal scanning line at which the pulse is removed is fixed in the position of every sixth horizontal scanning line on the basis of, for example, the 16th horizontal scanning line from the vertical synchronizing signal (the reset signal). If a video image is presented as shown in FIG. 4A, then a picture processed by the removal of the horizontal scanning lines becomes as shown in FIG. 4B, in which the oblique straight line shown in FIG. 4A is distorted in a stepwise fashion as shown in FIG. 4B. Further, since the position of the horizontal scanning line removed is fixed with respect to successive frames of the television image as described above, these stepwise-distorted portions become very conspicuous.
Furthermore, if a still picture is zoomed or if it is moved upward or downward, the zooming speed or the moving speed of the picture is varied at the position in which the horizontal scanning line is removed, thus resulting in a flicker being produced at the boundary portion of the picture, etc. This flicker deteriorates the image quality considerably.